Email: utku att aydonat dott net
Current Work Info: Principal Engineer at Tenstorrent Inc. Developping the software stack for a custom ASIC architecture targeting AI applications.
Intel Corp. : Between 2016-2018, I was a lead engineer responsible for architecting an AI accelerator hardware on the FPGA, and building the software stack that maps and optimizes neural network applications for this accelerator.
Intel (ex Altera) Corp. : Between 2011-2016, I worked as a senior engineer on Altera's OpenCL compiler. I developped compiler optimizations to efficiently map applications onto the FPGA.
Bachelor of Science: I received my B.Sc. degree in Electrical and Electronics Engineering from the Department of Electrical and Electronics Engineering, Middle East Technical University, Ankara, Turkey.
Interests: Compilers, neural networks and AI, parallel architectures, high-level design for FPGAs, multi-threading, transactional memory.
Ph.D. Thesis Topic: I designed a relaxed concurrency control algorithm that reduces abort rates in transactional memory (TM) systems. I implemented the algorithm in a real software TM system and in a simulator of a hardware TM system. (abstract.txt)
M.A.Sc. Thesis Topic: I designed and implemented an optimizing compiler for a multimedia SoC architecture. (abstract.txt)
Czajkowski, T.S.; Aydonat, U.; Denisenko, D.; Freeman, J.; Kinsner, M.; Neto, D.; Wong, J.; Yiannacouras, P.; Singh, D.P., "From opencl to high-performance hardware on FPGAS," Field Programmable Logic and Applications (FPL), 2012 22nd International Conference on , vol., no., pp.531,534, 2012
U. Aydonat and T.S. Abdelrahman, " Parallelization of Multimedia Applications on the Multi Level Computing Architecture," Journal of Embedded Computing (JEC) , Volume 4, Number 3-4, pp. 87-106, 2012.
U. Aydonat and T.S. Abdelrahman, " Relaxing Concurrency Control in Transactional Memory," Journal of IEEE Transactions on Parallel and Distributed Systems (TPDS) , Volume 23, Issue 7, pp. 1312-1325, July 2012.
Ph.D. Thesis, " Relaxing Concurrency Control in Transactional Memory.", January 2011.
U. Aydonat and T.S. Abdelrahman, " Hardware Support for Relaxed Concurrency Control in Transactional Memory," IEEE/ACM International Symposium on Microarchitecture (MICRO), pp. 15-26, 2010. [ Presentation ]
U. Aydonat and T.S. Abdelrahman, " Hardware Support For Serializable Transactions: A Study of Feasibility and Performance," Workshop on Transactional Computing (TRANSACT), 2009.
U. Aydonat and T.S. Abdelrahman, " Serializability of Transactions in Software Transactional Memory," Workshop on Transactional Computing (TRANSACT), 2008.
U. Aydonat and T.S. Abdelrahman, " Parallelization of Multimedia Applications on the Multi-Level Computing Architecture," Parallel and Distributed Computing and Systems (PDCS), pp. 438-447, 2006. [ Best Paper Award in Applications ]
M.A.Sc. Thesis, " Compiler Support for a Multimedia System-on-a-Chip Architecture.", April 2005.
F. Karim, A. Mellan, A. Nguyen, U. Aydonat and T.S. Abdelrahman, "A Multi-Level Computing Architecture For Multimedia Applications," IEEE Micro, vol. 24, no. 3, pp. 55–66, May–June 2004. Also appears in ST Journal of Research, vol. 1, no. 2, pp. 4–16, 2004.
F. Karim, A. Mellan, U. Aydonat, T.S. Abdelrahman, Bernd Stramm and A. Nguyen, "The Hyperprocessor: A Template System-on-Chip Architecture For Embedded Multimedia Applications," Workshop on Application Specific Processors, pp. 66-73, 2003.
I have served as teaching assistant for these courses:
Computer Architecture (ECE452)
Programming Fundamentals (ECE244 and ECE106)
Operating Systems (ECE344)
Computer Organization (ECE371 and ECE243)
Digital and Computer Systems (ECE253)